Numerous integrated circuit devices, structures and techniques of fabricating same, are known to the prior art. The following prior art patents and summaries are submitted to generally represent the state of the art.
Reference is made to U.S. Pat. No. 3,852,127 entitled "Method of Manufacturing Double Diffused Transistor with Base Region Parts of Different Depths" granted Dec. 3, 1974 to J. S. Lamming.
Reference is made to U.S. Pat. No. 3,881,242 entitled "Method of Manufacturing Semiconductor Devices" granted May 6, 1975 to R. Nuttall et al.
Reference is made to U.S. Pat. No. 3,904,450, entitled "Method of Fabricating Injection Logic Ingtegrated Circuits Using Oxide Isolation" granted Sept. 9, 1975 to W. J. Evans et al.
Reference is made to U.S. Pat. No. 4,006,046 entitled "Method For Compensating for Emitter-Push Effect in the Fabrication of Transistors" granted Feb. 1, 1977 to P. C. Pravin.
Reference is made to U.S. Pat. No. 4,007,474 entitled "Transistor Having An Emitter with A Low Impurity Concentration Portion and A High Impurity Concentration Portion" granted Feb. 18, 1977 to H. Yagi et al.
Reference is made to U.S. Pat. No. 4,080,619 entitled "Bipolar Type Semiconductor Device" granted Mar. 21, 1978 to K. Suzuki.
Reference is made to U.S. Pat. No. 4,157,269 entitled "Utilizing Polysilicon Diffusion Sources and Special Masking Techniques" granted June 5, 1979 to T. H. Ning et al.
Reference is made to U.S. Pat. No. 4,160,991 entitled "High Performance Bipolar Device and Method for Making Same" granted July 10, 1979 to N. G. Anantha et al.
Reference is made to the following IBM Technical Disclosure Bulletin Publications: (1) "Method For Reducing The Emitter-Base Contact Distance in Bipolar Transistors" by C. G. Jambotkar, Vol. 19, No. 12, May 1977, pages 4601-4; and (2) "Stacking Poly-Silicon Devices For High Density LSI" by I. T. Ho and J. Riseman, Vol. 21, No. 12, May 1979, pages 48434.
Reference is made to the publication entitled "A New Polysilicon Process For A Bipolar Device--PSA Technology", by Kenji Okada et al., IEEE Transactions on Electron Devices, Vol. ED-26, No. 4, April 1979, page 385-389.
The present trend in semiconductor technology is toward large scale integration of devices with very high speed and very low power dissipation. To achieve this, it is essential that the devices be made as small as possible by (a) making the vertical junction structure shallower, and (b) reducing the horizontal geometry. Precise shallow-junction profiles can be achieved with ion implantation of dopant species and their subsequent annealing with a thermal cycle. Device horizontal geometry depends to a large extent on the lithographic tools available. Within a given lithographic constraint, however, the use of a self-aligned process can greatly improve device performance.
In a conventional (non self-aligned) process, the transistor base area must be large enough to allow for the opening of base and emitter contacts, plus sufficient leeway for the misregistrations of contacts to doped regions. Since the base area and hence the base-collector junction capacitance is a very important parameter in the performance of very fast devices, it is necessary to reduce this base area to the minimum possible value. The use of a self-aligned polysilicon base process is a powerful technique in this respect, since it (a) allows self-registration of the emitter implant to the polyslicon base contact, and (b) allows the metal base contact to be moved from the device base area onto the polysilicon, thus reducing the device base area.